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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
MMCM Switching Characteristics
Table 39: MMCM Specification
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
MMCM_F INMAX
MMCM_F INMIN
Maximum Input Clock Frequency
Minimum Input Clock Frequency
1066.00
10.00
933.00
10.00
800.00
10.00
800.00
10.00
800.00
10.00
MHz
MHz
MMCM_F INJITTER
Maximum Input Clock Period Jitter
< 20% of clock input period or 1 ns Max
MMCM_F INDUTY
MMCM_F MIN_PSCLK
MMCM_F MAX_PSCLK
MMCM_F VCOMIN
MMCM_F VCOMAX
Allowable Input Duty Cycle: 10–49 MHz
Allowable Input Duty Cycle: 50–199 MHz
Allowable Input Duty Cycle: 200–399 MHz
Allowable Input Duty Cycle: 400–499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Dynamic Phase Shift Clock
Frequency
Maximum Dynamic Phase Shift Clock
Frequency
Minimum MMCM VCO Frequency
Maximum MMCM VCO Frequency
25.00
30.00
35.00
40.00
45.00
0.01
550.00
600.00
1600.00
25.00
30.00
35.00
40.00
45.00
0.01
500.00
600.00
1440.00
25.00
30.00
35.00
40.00
45.00
0.01
450.00
600.00
1200.00
25.00
30.00
35.00
40.00
45.00
0.01
450.00
600.00
1200.00
25.00
30.00
35.00
40.00
45.00
0.01
450.00
600.00
1200.00
%
%
%
%
%
MHz
MHz
MHz
MHz
MMCM_F BANDWIDTH
Low MMCM Bandwidth at
High MMCM Bandwidth at
Typical (1)
Typical (1)
1.00
4.00
1.00
4.00
1.00
4.00
1.00
4.00
1.00
4.00
MHz
MHz
MMCM_T STATPHAOFFSET Static Phase Offset of the MMCM
Outputs (2)
0.12
0.12
0.12
0.12
0.12
ns
MMCM_T OUTJITTER
MMCM Output Jitter
Note 3
MMCM_T OUTDUTY
MMCM_T LOCKMAX
MMCM_F OUTMAX
MMCM Output Clock Duty Cycle
Precision (4)
MMCM Maximum Lock Time
MMCM Maximum Output Frequency
0.20
100.00
1066.00
0.20
100.00
933.00
0.20
100.00
800.00
0.20
100.00
800.00
0.25
100.00
800.00
ns
μs
MHz
MMCM_F OUTMIN
MMCM Minimum Output
Frequency (5)(6)
4.69
4.69
4.69
4.69
4.69
MHz
MMCM_T EXTFDVAR
External Clock Feedback Variation
< 20% of clock input period or 1 ns Max
MMCM_RST MINPULSE
MMCM_F PFDMAX
MMCM_F PFDMIN
Minimum Reset Pulse Width
Maximum Frequency at the Phase
Frequency Detector
Minimum Frequency at the Phase
Frequency Detector
5.00
550.00
10.00
5.00
500.00
10.00
5.00
450.00
10.00
5.00
450.00
10.00
5.00
450.00
10.00
ns
MHz
MHz
MMCM_T FBDELAY
Maximum Delay in the Feedback Path
3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold
T MMCMDCK_PSEN /
T MMCMCKD_PSEN
T MMCMDCK_PSINCDEC /
T MMCMCKD_PSINCDEC
Setup and Hold of Phase Shift Enable
Setup and Hold of Phase Shift
Increment/Decrement
1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00
1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00
ns
ns
T MMCMCKO_PSDONE
Phase Shift Clock-to-Out of PSDONE
0.59
0.68
0.81
0.81
0.78
ns
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
T MMCMDCK_DADDR /
T MMCMCKD_DADDR
DADDR Setup/Hold
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00
ns, Min
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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